This is incorrect. AFAIK, at least most RISC CPUs have hardwired
control. I haven't done CPU design in 5 years (that CPU is now
available at your local Target store running a Sony Playstation), but
ours and all of MIPS' through the R4000 were hardwired. As were the
SPARC chips of the time (those even used automatic place-and-route for
the datapath: ugh!).