Re: tech snippets

Dejan Vucinic (
Wed, 25 Dec 1996 19:59:32 -0600

> E.g., consider a minor novely, the L4 nanokernel. It is just 12 kBytes,
> which vastly increases its probability to be at last in the 2nd-level
> cache if it is needed, hot-spot 1 kByte of message-passing code (one
> order of magnitude more efficent than Mach) will typically even reside in
> 1st-level cache. The microkernel is not portable, so why not writing it in
> assembly for each individual CPU? This should take a single person several
> months, which is tolerable. But consider the performance increase!
> Taking this one step further: why not putting the entire microkernel/VM
> into a _normal_ on-die SRAM, having an address in address space (cache
> has none, it occupies the same address space as the addressable core)?

Taking this yet another step further:
Over the last fifteen years all major CPU makers have migrated from
a monolithic design to microcode. Why in the world doesn't Motorola
or MIPS or whoever implement both x86 and 68000/PowerPC/MIPS instruction
set in a single chip!? Switch between the two with a protected
instruction. Run DOS on an SGI machine as a native OS, for
applications' sake. Have a nice safe MMU to go with it. Bury the
inferior Intel architecture. Later you can have the entire nanokernel
in the microcode if the approach works. The on-chip memory can only
increase with time. What am I missing? Grand OS Unification, heh. :)