Re: Blue Gene

Robert J. Bradbury (
Mon, 6 Dec 1999 20:15:45 -0800 (PST)

On Mon, 6 Dec 1999, Mike Hall wrote:

> I think the limited instruction set refers not to application design, but to
> processor architecture. My own take on this is that they are developing an
> ultra-reduced instruction set processor to maximize hardware speed, by
> reducing the overhead of fetching and decoding instructions prior to
> execution to a minimum, and eliminating complex instructions which invoke
> microcode routines.

I'd strongly question this. If they are taking an example out of the GRAPE book, they are designing the instructions for molecular modeling. As Eugene points out, when you get down to the quantum level there may still be problems with our shortcuts on the math or the granularity of current simulations. Molecular modeling (like galactic gravity calculations) aren't tremendously complicated, but the propagation of the effects through all of the data elements requires a very good architecture.

If you're an atom and I'm an atom, then I can push you, pull you or side-step you. Its a little more complicated due to the multiple types of pull (ionic, covalent, etc.) I can exert on you but it doesn't require a lot of instructions. It just requires that those instructions be very efficient and very accurate. From the sounds of it the additional instructions are going to get used for stuff like really high levels of multi-threading (they seem to be taking a page out of Tera's book here, since Tera is the first architecture I know of thats designed to thread switch in every instruction), and perhaps dealing with some of the fault tolerance stuff. You probably need the thread switching to allow you to keep doing something while waiting for information from off-chip CPUs. They may have sat back after doing the molecular modeling stuff and said, ok, now how can we turn the machine into a good data-mining computer, or a good speech recognition processor, or a good image processor and added some more instructions to round things out.

I don't think they took a R-RISC approach at all, but time will tell. I'd agree that there isn't any microcode in this, all the instructions should be done in hardware.