Re: Moore's law

Dan Clemmensen (
Sat, 27 Jun 1998 19:45:18 -0400

Michael Nielsen wrote:
> Playing Devil's Advocate here...
No problem with devil's advocacy. Please take my responses constructivly
and not as an argument. As I see it, we are exploring the problem
> On Fri, 26 Jun 1998, Dan Clemmensen wrote:
> > Michael Nielsen wrote:
> > >
> > > Storing stuff in 3-d gives rise to a large dissipation problem.
> > > Heuristically, the problem is that the heat generated goes like length
> > > cubed (total number of components), while heat dissipated goes like
> > > length squared (proportional to the surface area). As I've stated
> > > elsewhere, the reversible compution solution to this problem has a large
> > > potential hurdle to overcome, in the form of heat generated by error
> > > correction, which suffers the same probelm re dissipation.
> > >
> > I was referring to storage density, not storage speed. Nanomechanical
> > storage systems should require no power unless bits are being read or
> > written, so power dissipation is a function of I/O speed.
> Okay. There is still a slight issue in that addressing is a major
> overhead in storage architecture, and involves dynamics; the same caveats
> about the need for error correction apply. You also better make sure
> that your nanomechanical storage is extremely error free. What happens
> if thermal fluctuations flip your bit? Sure, this would be a rare event --
> but you're talking about a scenario where the goal is ~ 10^10 bits or more.

Addressing in a nanomechanical system occurs only as part of a read or write
operation. When no I/O is occurring, no energy is dissipated. Dissipation per
access depends on the size of the memory, O(logN) for random access,
which is negligible and is mitigated further by caching.
> > Three-dimensional
> > storage in a nonomechanical system, using 100 atoms per bit alllows
> > a fair number of extra atoms for "overhead" functions such as support
> > and heat-conduction. The energy dissipated to read or write a bit
> > nanomechanically should be very small compared to that needed by current
> > technology,
> Well, it would need to be. Suppose (conservatively), that you are going
> to have 10^6 layers, each storing bits with a density of 100 atoms / bit;
> a storage density of 1 bit for every few nanometers squared. Such a
> device will have roughly 10^12 more bits stored on it than current
> commerical chips. I forget the exact numbers, but the dissipation rate
> per logical operation is something like 10^6 kT in current chips. That
> means you have a major problem unless everything is done completely
> dissipation free.
I'm not sure that 10^6 layers is conservative. It's nanomechanically conservative
from a static structural standpoint (i.e., we could build it) but not from a
Moore's Law standpoint. We started this discussion with Moore's law in 2020.
Moore's law ( in one form) calls for doubling density every 1.5 years, or roughly
an increase of 16,000 by 2020. I can get this with an areal decrease from the current
10^6 nm^2/bit to 50 nm^2/bit without going into the third dimension at all. It's not
unreasonable to assume a decrease in energy per I/O on the same order, so I don't
have to invoke any of the other mechanisms.

If I operate the memory at the same access rate, the size of the memory is irrelevant.
If I operate the memory a 1000 times faster but using 1000 times less energy per I/O, I
have the same dissipation per volume. If I can sustain temperatures 3 times higher
(measured in degrees Kelvin above ambient) I can dissipate 81 times as much heat per
surface area. If my internal thermal conductivity is four times higher, I can
dissipate an additional four times the power, depending on geometry.

> > and diamondoid should be able to operate at much higher
> > temperatures than silicon-based devices. Diamondoid is a much better conductor
> > of heat than silicon, also.
> These are good points, but they only buy you a tiny amount.

As you see from the above, these points can affect the densities by a factor
of ten to one hundred or so. By contrast, you raise the issue of error correction.
However, even very powerful ECC schemes require less than doubling the amount
of volume needed to store a word. For example, use 13 bits to store a byte, and you
can perform error-correction on any single-bit error. As the word size goes up,
the percentage of extra bits needed goes down.