TI's new superDSP TMS320C6x is soon out. According to TI, DSP market will
grow from 2.3 G$ in 1996 to >8 G$ by 2000, whereas x86 zombie will
"only" double from current 17 G$. Hence TI has abandoned its x86 clone
project.
The wonder DSP runs at 0.2 GHz, boasts 8 parallel VLIW units (2
load/store, two multipliers, four units for integer ALU and jumps. As in
MMX, the maths can work with saturation. Each unit has a 1 OPs/clock
throughput, claiming 1.6 GOPs top numbers (TI says 1.2 is realistic). The
CPU has 32 x 32 bit registers in two files, but only 16 multiplication.
It has 128 kByte RAM, also usable as cache. Also there is a
SDRAM/SRAM/SBSRAM interface, two DMA channels, two timers, two serial
lines and a 16 bit host access port. The core (sans RAM) is just 0.55
MTransistors big. TI has an optimizing C++ compiler developed, offering
about 60%hand-crafted assembly efficiency. The architecture (dubbed
VeliciTI) is FLIW (flexible Long Instruction Word), a variable-length
word architecture (1-8 parallelly executed ops). C6x can serve 15 V.34
channels simultaneously/can do a 1024-integer-coefficient-FFT in 70 us. It
will be available in the second quarter of 1997 for $96 (25 kpcs quantity).
Sounds good, huh? Hang Wintel! ciao, 'gene
P.S. Now Linux' XFree86 knows Matrox Milennium (_not_ Mystique) at 1
Mxstones, and Virge as well (pretty lousy 2d acceleration though, methinks).