Re: COMP: Re: tech snippets

Eugene Leitl (
Wed, 1 Jan 1997 22:45:53 +0100 (MET)

On Sun, 29 Dec 1996, Mark Grant wrote:

> On Sat, 28 Dec 1996, Eugene Leitl wrote:
> > It depends. On your programming style, e.g. I was argumenting from the
> > position of tiny grain sizes (WSI constraint), and an asychronous OOP
> > with high call density, aka threaded code (tiny grains need dense code).
> I hate to say it, but to me you seem to be recreating the transputer; a

So what? It was a great architecture, killed only by desastrous marketing
and one Maggie T. (well-meant but untimely privatization programme, Inmos
being one of the more prominent victims. Well, Englishmen and the
French... ARM (and StrongARM) is very nice, though. Ah, and that
stillborn Helios by Tim King. The Abacus. The Amiga transputer
card. c't's DIY transputer box. Nostalgy!).

> standalone chip with fast task-switching, limited memory protection (at
> least for the T9000) and messaging built into the hardware (or SRAM in the
> CPU in your case).

Actually, no. The transputer was way too bloated for my taste, the
architecture a far cry from being minimalistic. What I like about the
transputer is that it had on-die RAM and links (but too slow, too few,
and no crossbar, so + + + ).

> > Effectively yes, but it is slower, and the machinery is still there --
> > on-die transistors are not cheap.
> True... but your processor is presumably going to have its own on-chip
> cache? So just make it 12k larger to make room for the nanokernel. If you

Nope, no cache. Few kByte SRAM to fit the essentials, and 128 kByte DRAM,
but no cache. NO cache. No FPU. No nothing. Rank wie Windhunde.

> have separate SRAM you're still going to need extra hardware for the
> address decoding. The speed should be identical to on-chip SRAM; that's

Cache logic vs. address decoding? Another weight league entirely. Cache
(in this particular supercalifragiminimalistic architecture) has bad
price/performance ratio.

> why the T9000 design had this capability. The earlier chips had on-chip

Another reason why it never quite got off ground. Admit it, it IS mythical.

> SRAM for performance reasons (instant access rather than six cycles to get
> data from DRAM), and because embedded applications could run with just a

On-die DRAM is a lot faster, since no signal upscaling is required.

> ROM and transputer, solely using internal RAM.
> > T9000 is mythical, anyway.
> Well, I went to the official launch about five years ago and it wasn't
> ready (pretty bizarre), but I remember reading Usenet articles from people
> who had some. Not that it would be very competitive today anyway.

Alas, that the one big minus of them transputers: they botched the launch
and never updated the family. Intel had it really easy back then.
Speaking of that, Intel has it still easy as $\pi$.

> Mark