> It depends. On your programming style, e.g. I was argumenting from the
> position of tiny grain sizes (WSI constraint), and an asychronous OOP
> with high call density, aka threaded code (tiny grains need dense code).
I hate to say it, but to me you seem to be recreating the transputer; a
standalone chip with fast task-switching, limited memory protection (at
least for the T9000) and messaging built into the hardware (or SRAM in the
CPU in your case).
> Effectively yes, but it is slower, and the machinery is still there --
> on-die transistors are not cheap.
True... but your processor is presumably going to have its own on-chip
cache? So just make it 12k larger to make room for the nanokernel. If you
have seperate SRAM you're still going to need extra hardware for the
address decoding. The speed should be identical to on-chip SRAM; that's
why the T9000 design had this capability. The earlier chips had on-chip
SRAM for performance reasons (instant access rather than six cycles to get
data from DRAM), and because embedded applications could run with just a
ROM and transputer, solely using internal RAM.
> T9000 is mythical, anyway.
Well, I went to the official launch about five years ago and it wasn't
ready (pretty bizarre), but I remember reading Usenet articles from people
who had some. Not that it would be very competitive today anyway.
Mark
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