Nanotechnology, organics advance toward IEDM
By Nicolas Mokhoff
(10/06/00, 5:29 p.m. EST)
SAN FRANCISCO - Advances in nanotechnology and organic electronics
will complement mainstream silicon process developments at the
International Electron Devices Meeting Dec. 11-13.
A team from Japan's NTT research laboratories has gone beyond the
realm of single-transistor devices to build the first elemental
circuit using single-electron transistors. The team fabricated the
circuit using a silicon-on-insulator (SOI) process and a vertical
pattern-dependent oxidation technique. When operating at 25 K, the
circuit performed basic arithmetic calculations.
Nanotechnology is also being applied to nonvolatile memory devices,
where nanocrystals on a floating gate are used in place of capacitors
to store the charge. A research team at Lucent Technologies has used
an aerosol-based technique to deposit and integrate a thin, uniform
layer of nanocrystals in the gate dielectric of 200-nanometer
MOSFETs. The 3-nm-diameter spherical nanocrystals were fabricated from
diluted silane, heated to 950 degrees C.
Researchers at the University of California at Berkeley are scheduled
to report at the San Francisco meeting on what they say is the
smallest transistor gate ever built: 20 nm, with an ultrathin,
140-angstrom silicon-on-insulator layer. The researchers overcame the
unwanted series resistance often encountered in thin layers of SOI by
optimizing the silicide process step on the transistor's contacts. The
work is one more indication of how SOI is being applied to mainstream
Meanwhile, in the race for speedy transistors, Hitachi Ltd.
researchers claim to have built the fastest silicon-based bipolar
transistor, operating at 180 GHz with an ECL gate delay of 6.7
picoseconds. The self-aligned, 200-nm transistor was built using
silicon germanium and is compatible with standard CMOS
architectures. It is said to be the first transistor built in this
high-resistance material to incorporate passive components - a
capacitor and a high-Q inductor.
A team from Canada's Simon Fraser University will detail an
indium-phosphide-based double-bipolar-transistor heterostructure fast
enough to be used with 40-Gbit/second fiber-optic systems. The
researchers claim to have overcome a collector-blocking effect that
has been the bane of base-collector heterojunction designs for
years. The devices achieve a peak cutoff frequency of 250 GHz, claimed
to be the fastest to date for a double heterostructure design.
Transistors via ink-jet
Finally, researchers at Cambridge University will describe the
production of all-polymer thin-film transistors using a
high-resolution ink-jet printer, a first for that production process.
While ink-jet techniques have been used to build polymer LEDs and
large, flexible displays, they have not been applied to manufacture
transistors. Cambridge researchers used a piezoelectric ink-jet print
head to build the transistors with a channel length of 5 micrometers
and a patterned gate electrode. The devices showed on/off current
ratios exceeding 105 and electron mobilities of 0.02 cm squared/Vs,
adequate for many electronics applications.
A panel discussion will consider what technologies will take the
industry past the 40-Gbit/s range. Other panels will focus on
alternative memory architectures and single-electron transistors.
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