Eugene Leitl wrote:
> These are simulated neurons. They
> dwell as 3d patterns in RAM. The FPGA reads from, mangles, and writes
> RAM contents back. Because the FPGA is not integrated into the RAM
> die, it can only access a tiny fraction of it simultaneusly.
That isn't quite how I read it. My understanding is that they encode the
configuration and state information for each FPGA-sized block of simulated
neurons in a rather tiny block of binary data, which can be moved to or from
regular memory in less than one of the FPGA chip's clock cycles. Their
limitations are that each FPGA can simulate only a very few neurons, so they
have to do the time-sharing trick to avoid having to buy millions of the
things. To improve performance they have to get more FPGAs, get denser
FPGAs so they can put more neurons on each of them, or crank up the speed at
which the FPGAs run.
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