Robert Bradbury writes:
> The current chips (at the 0.18 micrometer scale) are using lines
> that are roughly 360 atoms wide (which isn't very wide when you
> think about it...).
Yeah, the chiefest reason why Moore may suddenly deviate from the
straight log plot. Of course one can increase performance without
increasing integration density, by changing architecture (embedded
(on-die) DRAM with ultrawide buses and low latencies), and increasing
the die yield (smaller dies -> higher yield, with small enough dies
wafer-scale integration).
After these have been exhausted, molecular-circuit nano better be
ready, orelse.
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